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Title: 高濃度鋯之鐵電氧化鉿鋯極化反應及多階操作
Polarization Response and Multi-Level Operation for Ferroelectric HfZrO2 with High Zirconium Content
Authors: 李敏鴻
Tseng, Yi-Ju
Keywords: 氧化鉿鋯
Multi-Level operation
Issue Date: 2020
Abstract: 近幾年來在半導體的領域中,鐵電材料是非常盛行及熱門的研究主題,而鐵電氧化鉿鋯(Hf1-xZrxO2, HZO)也已被廣泛的利用,本論文將選擇摻雜高濃度鋯之HZO作為鐵電電晶體的絕緣層材料,進行其特性的研究及應用。 鐵電材料的遲滯現象(Hysteresis)具有雙穩態的特性,滿足負電容電壓放大(Negative capacitance, NC)和記憶體儲存信號的要求,本論文將以鐵電極化反應時間量測來驗證高濃度鋯之HZO鐵電電晶體的負電容效應,且將AFE(Anti-Ferroelectric)-HZO材料製作成金屬鐵電層金屬(Metal-Ferroelectric-Metal, MFM)電容結構及金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET),分別進行相關電性的研究。 由於現今電晶體不斷微縮,VDD也隨之下降。透過使用具有不同功函數的上下電極材料在MFM中會產生內建偏壓讓Zr為90%之AFE原始遲滯曲線偏移並產生兩個穩定的非揮發性狀態達到降低功耗的效果。此外,透過打入脈衝電壓可將Zr為75%的FET分為四階狀態,等效的增加了記憶體晶片密度。於記憶體可靠度方面,Retention可以保持到104秒,Endurance則是可操作至106個週期。
In the past decades, ferroelectric materials have attracted growing interest and have been extensively investigated to leverage state-of-the-art CMOS architectures. In this work, zirconium high concentration HfZrO2 as the gate insulator of FeFET is studied for its characteristics. The bi-stable state nature feature of hysteresis loops from ferroelectric materials satisfies the demands of storing signal for memory and voltage amplification concept for negative capacitance. The electrical properties of zirconium high concentration HfZrO2 applied on Metal-Ferroelectric-Metal (MFM) and Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) are demonstrated, respectively. In addition, negative capacitance effect is validated by Q-VFE of voltage transient response measurement. Due to the continuously scaling of transistors, VDD reduction has also accompany. By employing top and bottom electrodes with different work functions, a built-in bias is generated in MFM. This bias induced the original hysteresis loop shift of 90% Zr content AFE and enables two stable non-volatile states to meet power consumption reduced. Moreover, four-level states are achieved by 75% Zr content HZO FET when pulse voltage applying, and effectively increase the memory chip density. For reliability of memory operation, data retention up to 104s and endurance surpass 106 cycles both are obtained.
Other Identifiers: G060777006H
Appears in Collections:學位論文

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