以Generalized Hebbian Algorithm 為基礎的主成分分析之硬體實現
Abstract
本論文針對主成分分析(principle component analysis, PCA)提出一個以generalized Hebbian algorithm (GHA)為基礎的硬體架構。在此硬體架構中，我們讓負責突觸權重向量(synaptic weight vectors)更新的部分分為若干個層級(stages)，前一個層級所計算出來的結果將傳送至下一個層級使用，來達到加快訓練速度以及降低面積成本(area cost)的目的。本文所提出的硬體架構已實作並嵌入於可程式化系統晶片(system-on-programmable-chip, SOPC)之平台。由實驗結果顯示，此硬體架構是一種有效且可代替主成分分析之運算，亦能獲得高性能與低計算時間之結果。
This paper presents a novel hardware architecture for fast principle component analysis (PCA). The architecture is based on generalized Hebbian algorithm (GHA). In the architecture, the updating of different synaptic weight vectors are divided into a number of stages. The results of precedent stages will be used for the computation of subsequent stages for expediting training speed and lowering the area cost. The proposed architecture has been embedded in a system-on-programmable-chip (SOPC) platform for physical performance measurement. Experimental results show that the proposed architecture is an effective alternative for fast PCA attaining both high performance and low computational time.
This paper presents a novel hardware architecture for fast principle component analysis (PCA). The architecture is based on generalized Hebbian algorithm (GHA). In the architecture, the updating of different synaptic weight vectors are divided into a number of stages. The results of precedent stages will be used for the computation of subsequent stages for expediting training speed and lowering the area cost. The proposed architecture has been embedded in a system-on-programmable-chip (SOPC) platform for physical performance measurement. Experimental results show that the proposed architecture is an effective alternative for fast PCA attaining both high performance and low computational time.
Description
Keywords
Generalized Hebbian Algorithm, 主成分分析, 可程式化系統晶片, 現場可編程邏輯閘陣列