蔡政翰Tsai, Jeng-Han郭胤廷Kuo, Yin-Ting2019-09-032019-07-312019-09-032015http://etds.lib.ntnu.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=id=%22G060275001H%22.&%22.id.&http://rportal.lib.ntnu.edu.tw:80/handle/20.500.12235/95612近年來由於市場需求及半導體製程的進步，無線通訊產業愈來愈發達，而隨著操作頻率不斷的提升，使得高頻積體電路(Integrated-circuit, IC)的設計逐漸被重視。對於系統電路而言，不論是數位類比或是射頻應用，都需要一個時脈產生器來提供穩定且精確的訊號源，來維持系統正常運作。本論文以射頻收發系統中所需的本地振盪器為應用範疇，實現了三個不同頻段的時脈產生電路，分別為400 MHz鎖相迴路、K頻帶電壓控制振盪器以及X頻帶頻率合成器。 第三章實現了400 MHz的鎖相迴路，其中電壓控制振盪器採用了差動式的環型架構，降低雜訊的干擾，而輸入端部分加入了偏壓電路，提供延遲單元所需的負載偏壓和電流源偏壓，減少外部供應電源的使用及外部電源雜訊的干擾。除頻器的設計則是採用真單相時脈(True single phase clocking, TSPC)架構，來達到較低的消耗功率與較小的晶片占用面積。本次電路設計的量測結果，其鎖定頻率範圍為224 ~ 448 MHz，相位雜訊在載波偏移100 kHz處約-98 dBc/Hz，在載波偏移10 MHz處約-115 dBc/Hz。整體電路的消耗功率約為2.62 mW。包含pad之晶片總面積大小為0.55 × 0.6 mm^2 。 第四章實現了K頻帶的電壓控制振盪器，採用NMOS交錯耦合對之LC共振式架構，為了降低輸出相位雜訊，在共振腔內加入了一個定電容，減少電感使用以提升整體共振腔的品質因素。此外，為了避免負載效應影響操作頻率及特性，在主電路輸出端加入共源極組態的緩衝放大器，並將汲極電阻以電感來替換，減少電阻性損耗以降低雜訊影響。本次量測分別以高電壓和低電壓兩種情況來比較特性。在高電壓時(VDD = 1 V)，調頻範圍約為23.1 ~ 23.38 GHz，相位雜訊在載波偏移1 MHz處約-109.04 dBc/Hz，包含輸出緩衝器的功率消耗約為21 mW，優異指數(Figure of merit, FoM)約-185.79 dBc/Hz；而低電壓(VDD = 0.65 V)時，調頻範圍約為23.51 ~ 23.77 GHz，相位雜訊在載波偏移1 MHz處約-106.02 dBc/Hz，包含輸出緩衝器的功率消耗約為10.62 mW，FoM則可達到約-189.76 dBc/Hz。包含pad之晶片總面積大小為0.45 × 0.625 mm^2。 第五章實現了X頻帶的頻率合成器，以Ku頻帶的低雜訊降頻器(Low Noise Block down converter, LNB)作為應用，其振盪源輸出分別操作在9.75 GHz和10.6 GHz，因此為了達到頻段切換，在壓控振盪器的共振腔內加入了開關電路，並在NMOS交錯耦合對的源極端串聯一組電感來增加輸出訊號擺幅，以降低相位雜訊。多模除頻器則是採用串接七級的TSPC除2/3雙模數除頻架構，分別讓9.75 GHz及10.6 GHz降頻為輸入參考頻率。本次頻率合成器在低頻段時的鎖定頻率範圍為9.75 ~ 10.23 GHz，高頻段為10.35 ~ 10.89 GHz。相位雜訊部分，輸出為9.75 GHz時，載波偏移在100 kHz處約-51.66 dBc/Hz，在1 MHz處約-72.69 dBc/Hz，在10 MHz處約-114.9 dBc/Hz。輸出為10.6 GHz時，載波偏移在100 kHz處約-51.02 dBc/Hz，在1 MHz處約-67.91 dBc/Hz，在10 MHz處約-112.38 dBc/Hz。整體功率消耗在低頻段時約33.88 mW，高頻段則約36.68 mW。包含pad之晶片總面積大小為0.88 × 0.81 mm^2。As the operating frequency becomes higher and higher, the design of high-frequency integrated circuits is gradually being taken seriously. For system circuits, the clock generators provide a stable and accurate signal to maintain an expected operation. In this thesis, the clock generators applied in the local oscillators are implemented, respectively of 400 MHz phase-locked loop (PLL), K-band voltage -controlled oscillator (VCO) and X-band frequency synthesizer. In chapter three, a 400 MHz PLL has been designed and implemented. The ring-type differential VCO is adopted to reduce the noise, and the additional bias circuit is used for the delay cell to provide the required bias, which can reduce the external noise and the use of the power supply. To achieve low power consumption and smaller die area, a true single phase clocking (TSPC) divider is adopted. The measurement results show that the locking range of this PLL is 224 ~ 448 MHz. The phase noise is about -98 dBc/Hz at 100 kHz offset and -115 dBc/Hz at 10 MHz offset. Total power consumption is about 2.62 mW. The chip size including pads is 0.55 × 0.6 mm2. In chapter four, a K-band VCO has been designed and implemented. To improve the quality factor of the whole resonator, a NMOS cross-coupled pair with the capacitor combined is adopted. An output buffer of common-source configuration is connected from the core circuit to avoid the loading effect. Moreover, the drain resistor is replaced by the inductor to reduce resistive loss. The measurement results compare two cases of the high power voltage and low power voltage. In high voltage (VDD = 1 V), the tuning range is about 23.1 ~ 23.38 GHz, the phase noise is about -109.04 dBc/Hz at 1 MHz offset. The power consumption including the output buffer is about 21 mW. The figure of merit (FoM) is about -185.79 dBc/Hz. In low voltage (VDD = 0.65 V), the tuning range is about 23.51 ~ 23.77 GHz. The phase noise is about -106.02 dBc/Hz at 1 MHz offset. The power consumption including the output buffer is about 10.62 mW. The FoM is about -189.76 dBc/Hz. The chip size including pads is 0.45 × 0.625 mm2. In chapter five, an X-band frequency synthesizer has been designed and implemented for Ku-band low noise block down converter (LNB). From the specification, the operating frequency is 9.75 GHz and 10.6 GHz. In order to adjust the frequency band, the switching circuit is placed in the LC resonator. In addition, a pair of the inductors is in series to the source terminal of the NMOS cross-coupled pair to increase the output signal. The multi-modulus divider (MMD) uses fully TSPC ÷ 2/3 dual-modulus divider architecture with seven stages cascaded. In the low band, the measured locking range is 9.75 ~ 10.23 GHz, and in the high band, the locking range is 10.35 ~ 10.89 GHz. The phase noise at 9.75 GHz is about -51.66 dBc/Hz, -72.69 dBc/Hz and -114.9 dBc/Hz at 100 kHz, 1 MHz and 10 MHz offset, respectively. The phase noise at 10.6 GHz is about -51.02 dBc/Hz, -67.91 dBc/Hz and -112.38 dBc/Hz at 100 kHz, 1 MHz and 10 MHz offset, respectively. Total power consumption at low band frequency is about 33.88 mW, and about 36.68 mW in high band frequency. The chip size including pads is 0.88 × 0.81 mm2.時脈產生器鎖相迴路真單相時脈電壓控制振盪器LC調諧組態頻率合成器多模數除頻器clock generatorphase-locked looptrue single phase clockingvoltage-controlled oscillatorLC resonancefrequency synthesizermulti-modulus divider