An ultra low-power 24 GHz phase-lock-loop with low phase-noise VCO embedded in 0.18-μm CMOS process

國立臺灣師範大學應用電子科技學系Yu-Hsuan LinJeng-Han TsaiYen-Hung KuoTian-Wei Huang2014-10-302014-10-302011-12-08http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/32261A 24 GHz 29.8 mW Phase-lock-loop using 0.18 μm CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by -122 dBc/Hz at 10 MHz offset with low supply voltage and equipped the locking range of 20.80-23.37 GHz. The PLL dissipate 29.8 mW (only 13.3 mW in VCO + ILFD) and occupies the total area of 0.39 mm2 without off-chip loop filter.CMOSPhase-Lock-Loop (PLL)VCOInjection-Locked Frequency Divider(ILFD).An ultra low-power 24 GHz phase-lock-loop with low phase-noise VCO embedded in 0.18-μm CMOS process