國立臺灣師範大學應用電子科技學系Jeng-Han TsaiChung-Han WuHong-Yuan YangTian-Wei Huang2014-10-302014-10-302011-12-011531-1309http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/32239A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power ampli- fier (PA) achieves a of 10.72 dBm and of 7.3 dBm from 1.2 V supply. After linearization, the has been doubled from 7.3 to 10.2 dBm and the operating PAE at consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.CMOSlinearizationlinearizerpower amplifier (PA)pre-distortion60 GHz.