黃文吉Wen-Jyi Hwang翁聖凱Sheng-Kai Weng2019-09-052011-7-242019-09-052009http://etds.lib.ntnu.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=id=%22GN0696470502%22.&%22.id.&http://rportal.lib.ntnu.edu.tw:80/handle/20.500.12235/106743本論文提出一個以Memetic Algorithm(MA)為基礎的向量量化器(VQ)硬體架構；此架構中以steady-state Genetic Algorithm (GA)做全域搜尋，並採用C-means演算法進行局部改善；硬體架構中包含族群記憶體單元(population memory unit)、交配突變單元(crossover and mutation unit)、C-means單元以及生存測試更新單元( survival test and update unit)；在架構中採用了以移位暫存器(Shift register)為基礎的交配突變單元，來加快交配突變運算的執行。除此之外，設計了一個pipeline架構來實現C-means單元；最後將MA電路結合軟核心(softcore)CPU並實際測量硬體電路效能。實驗的結果顯示，所提出的向量量化器(VQ)硬體架構對於VQ的最佳化是擁有高效能表現以及少量計算時間的優點。A novel hardware architecture for memetic vector quantizer (VQ) design is presented in this thesis. The architecture uses steady-state genetic algorithm (GA) for global search, and C-means algorithm for local refinement. It adopts a shift register based circuit for accelerating mutation and crossover operations in the steady state GA. It also uses a pipeline architecture for the hardware implementation of C-means algorithm. The proposed architecture has been embedded in a softcore CPU for physical performance measurement. Experimental results show that the proposed architecture is an effective alternative for VQ optimization attaining both high performance and low computational time.基因法則系統晶片設計向量量化器可程式化邏輯閘陣列GASOPCVQFPGA