國立臺灣師範大學電機工程學系Chien-Hung KuoChing-Shan ChienMeng-Feng LinYen-Cheng Tsai2014-10-302014-10-302007-07-04http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/32212In this paper, a fast-locking delay-locked loop (DLL)-based frequency multiplier for wide-range operation is proposed. A programmable charging circuit (PCC) to the loop filter is developed to accelerate the locking time of DLL. In the presented DLL, the pseudo-differential delay cell is adopted in the voltage-controlled delay line (VCDL) for the suppression of the common-mode noise. Five clock cycles of the least lock time can be reached in the presented DLL. A new DLL-based frequency multiplier with less active devices is also proposed to promote the operating frequency range from 200 MHz to 2.1 GHz. The simulated cycle-to-cycle jitter of the DLL is 31 ps at 320 MHz of the reference input. The prototype circuit has been fabricated in a 0.18 μm 1P6M CMOS technology. The core area excluding PADs is 0.36x0.37 mm2. The power consumption of the proposed DLL is 24 mW from a 1.8 V of supply voltage.Clock generatordelay-locked loops (DLLs)frequency multiplierprogrammable charging circuit (PCC)fast-locking DLL