國立臺灣師範大學電機工程學系Chien-Hung KuoHuai-Juan Xie2014-10-302014-10-302008-05-21http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/32215This paper presents a 0.8 V multibit delta-sigma (DeltaSigma) modulator with a single switched-opamp (SOP) in a 0.18 mum 1P6M CMOS technology. The double-sampling technique is adopted in the modulator to promote the clock efficiency and relax the requirement of SOP. To improve the accuracy of the multibit quantizer in a low-voltage circumstance and reduce the static power, a new switched-capacitor (SC) multibit quantizer without R-string is proposed. The presented DeltaSigma modulator achieves a signal-to-noise-plus-distortion ratio (SNDR) of 88 dB and dynamic range (DR) of 89 dB within a 22 kHz of bandwidth under a 1.25 MHz of clock rate. The power consumption of the presented modulator is 4.2 mW at a 0.8 V of supply voltage.