具備防止誤觸發機制之低漏電流靜電放電箝制電路

蔡政翰林群祐Tsai, Jeng-HanLin, Chun-Yu陳柏孝Chen, Po-Xiao2024-12-172026-08-012024https://etds.lib.ntnu.edu.tw/thesis/detail/ce028a612e2914b99f178e468946dae0/http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/122944具備防止誤觸發機制之低漏電流靜電放電箝制電路Low-Leakage Power-Rail ESD Clamp Circuit with False Trigger Prevention Mechanism學術論文