Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems

國立臺灣師範大學資訊教育研究所Fang, Sung-ChuanChang, Kuo-EnFeng, Wu-ShiungChen, Sao-Jie2014-10-302014-10-301991-03-010-89791-395-7http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/34400via minimizationlayer assignmentVLSI/PCB routingNP-completeConstrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems