探討金屬介面層應用於氧化鋯鉿鐵電記憶體之電性可靠度研究
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2024
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隨著科技進步,數據量急速增長,記憶單元與邏輯單元之間的數據傳輸面臨嚴重的功耗和訊號延遲問題,因此,結合記憶與邏輯單元的邏輯記憶元件(Logic in Memory)應運而生,其中鐵電記憶體(FeRAM)因高集成密度、低功耗、高讀寫速度而備受矚目。然而,受到製程條件與電場循環等因素影響,金屬-鐵電-金屬(Metal-Ferroelectric-Metal)鐵電電容在電極與鐵電層之間容易產生介面層缺陷,導致元件漏電流增加、極化特性降低與可靠度衰退等問題。因此,本研究調變氮化鈦的材料性質與厚度,將其作為下電極緩衝層、中間阻障層、上電極介面層與金屬介面層,應用於氧化鋯鉿鐵電電容之中,並通過量測分析,探討氮化鈦是否能穩定面品質、優化元件性能。實驗結果顯示,2奈米的氮化鈦作為下電極緩衝層與中間阻障層不僅未能增強鐵電極化特性,反而導致漏電流大幅提升,推測氮化鈦已經發生氧化反應。在氮化鈦金屬介面層電容結構中,通過調變氮化鈦金屬介面層厚度,可以在極化特性、漏電流與可靠度之間取得參數最佳化。經過450°C的金屬沉積後退火處理,氮化鈦金屬介面層電容結構展現最佳兩倍殘餘極化量24.83 µC/cm2,比起氮化鈦上電極介面層電容結構高出約16%~45%,氮化鈦金屬介面層電容結構在-3 V時的漏電流值為1.72×10-10A,顯著低於無氮化鈦金屬介面層電容結構約3個數量級。在可靠度測試中,無氮化鈦金屬介面層電容結構在較小的定電壓應力下便發生永久性崩潰,氮化鈦金屬介面層電容結構則需要更大的定電壓應力才會發生電洞生成現象,展現卓越的抗電應力,並且氮化鈦金屬介面層電容結構經過108次耐久度循環後仍維持兩倍殘餘極化量7.13 µC/cm2,表現出最低的疲勞現象,證實氮化鈦金屬介面層可以穩定氮化鉭上電極與氧化鋯鉿薄膜間的介面品質,減少介面缺陷的產生,有助於維持優異的極化特性、降低漏電流與優化元件可靠度。
With rapid technological advancement, increasing data volumes have caused significant power consumption and signal delay issues in data transmission between memory and logic units. Logic-in-Memory devices, which integrate logic and memory units, have emerged as a solution. Ferroelectric Random Access Memory is notable for its high density, low power consumption, and fast read/write speeds. However, process conditions and electric field cycling will lead to interface layer defects in Metal-Ferroelectric-Metal capacitors, resulting in increased leakage current, reduced polarization, and decreased reliability. Therefore, this study modifies the material properties and thickness of titanium nitride (TiN) for use as a bottom electrode buffer layer, inserting barrier layer, top electrode interface layer, and interface metal layer in hafnium zirconium oxide (HfZrO) ferroelectric capacitors to stabilize interface quality and optimize device performance.The results show that using 2 nm TiN as a bottom electrode buffer layer and inserting barrier layer did not enhance polarization but increased leakage current, likely due to TiN oxidation. However, optimizing the thickness of the TiN interface metal layer improved polarization characteristics, decreased leakage current, and enhanced reliability. After post-metal annealing at 450°C, the TiN interface metal layer capacitor achieved a double remanent polarization of 24.83 µC/cm², 16% to 45% higher than the TiN top electrode interface layer capacitor. Additionally, its leakage current at -3 V is 1.72×10-10A, three orders of magnitude lower than the capacitor without a TiN interface metal layer. In reliability tests, the TiN interface metal layer capacitor did not occur early breakdown, it showed superior resistance to constant voltage stress and maintained double remanent polarization of 7.13 µC/cm² with the lowest fatigue after 108 endurance cycles. These results confirm the TiN interface metal layer stabilizes the interface between the Tantalum nitride top electrode and HfZrO, reducing defect generation. At the same time, it optimizes device polarization, leakage current, and reliability.
With rapid technological advancement, increasing data volumes have caused significant power consumption and signal delay issues in data transmission between memory and logic units. Logic-in-Memory devices, which integrate logic and memory units, have emerged as a solution. Ferroelectric Random Access Memory is notable for its high density, low power consumption, and fast read/write speeds. However, process conditions and electric field cycling will lead to interface layer defects in Metal-Ferroelectric-Metal capacitors, resulting in increased leakage current, reduced polarization, and decreased reliability. Therefore, this study modifies the material properties and thickness of titanium nitride (TiN) for use as a bottom electrode buffer layer, inserting barrier layer, top electrode interface layer, and interface metal layer in hafnium zirconium oxide (HfZrO) ferroelectric capacitors to stabilize interface quality and optimize device performance.The results show that using 2 nm TiN as a bottom electrode buffer layer and inserting barrier layer did not enhance polarization but increased leakage current, likely due to TiN oxidation. However, optimizing the thickness of the TiN interface metal layer improved polarization characteristics, decreased leakage current, and enhanced reliability. After post-metal annealing at 450°C, the TiN interface metal layer capacitor achieved a double remanent polarization of 24.83 µC/cm², 16% to 45% higher than the TiN top electrode interface layer capacitor. Additionally, its leakage current at -3 V is 1.72×10-10A, three orders of magnitude lower than the capacitor without a TiN interface metal layer. In reliability tests, the TiN interface metal layer capacitor did not occur early breakdown, it showed superior resistance to constant voltage stress and maintained double remanent polarization of 7.13 µC/cm² with the lowest fatigue after 108 endurance cycles. These results confirm the TiN interface metal layer stabilizes the interface between the Tantalum nitride top electrode and HfZrO, reducing defect generation. At the same time, it optimizes device polarization, leakage current, and reliability.
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鐵電記憶體, 氧化鋯鉿, 氮化鈦金屬介面層, 可靠度測試, Ferroelectric Random Access Memory, HfZrO, Interface Metal layer, Reliability Test