一種驗證先進三閘極電晶體幾何變異之理論與實驗方法

Abstract

為了不斷的提高平面型金氧半場效電晶體(Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET)的性能，藉由縮短通道長度以及降低氧化層厚度來達成汲極飽和電流(Id,sat)的提升，因此產生了許多問題，如短通道效應(short channel effect)、閘極漏電流(gate leakage)的產生等，使得發展出擁有更好之閘極控制能力的三閘極鰭式電晶體(trigate FinFET)，卻又衍生出其鰭的高度提升下之幾何變動率(geometric variations)的問題。 本論文發展出了對於三閘極電晶體上幾何變動率的理論，包括了線(line)以及表面粗糙度(surface roughness)，而幾何變動率與氧化層厚度之變動率(oxide thickness variations)分別可由量測閘極電容與閘極電流得到，實驗結果顯示，三閘極電晶體在鰭的高度不斷提升下，受到了嚴重的幾何變動率的影響，其中氧化層表面粗糙度造成了介面缺陷的產生，以及電子遷移率的下降，進而導致提高了臨界電壓的變動率(Vth)，此外線粗糙度分別由邊線粗糙度(line edge roughness)以及線寬粗糙度(line width roughness)所組成，而三閘極電晶體顯示出更嚴重的邊線粗糙度，造成較大之汲極電流之變動率(Id)，並且發現於長通道中所引起的原因為蝕刻製程(etchant process)所致，於短通道中所引起的原因為不精確的曝光所致。這些研究成果，提供了一個具有量化且具有系統的研究方法，對於我們在未來對於三閘極電晶體設計及量產上，頗具參考價值。To improve the performance of MOSFET, the scaling of channel length and the oxide thickness will be able to increase the saturation current. But the additional problem including short channel and gate leakage are induced. On the other hand, trigate FinFET, which has a better gate controllability, creates another problem of geometric variations. A new theory has been developed for geometric variations, including not only line but also surface roughness, of trigate FinFETs. The geometric variation and oxide thickness variations can be measured from gate capacitance and current variations, respectively. Experimental results show that trigate devices are subject to serious geometric variations as the fin height scales up, among which surface roughness creates interface traps and induces mobility degradation, leading to a worse Vth variation. In addition, line roughness is decoupled into line-edge and line-width roughness. Trigate devices exhibit rough line edges, induced by etchant process in long-channel regime and by inaccurate lithography in short-channel regime, leading to larger drain-current variation. These results provide us a systematic and quantifiable approach to improve geometric variations in the design and manufacturing of future trigate devices.