Design and Verification for Dual Issue Digital Signal Processor

dc.contributor國立臺灣師範大學科技應用與人力資源發展學系zh_tw
dc.contributor.authorCheng-Hung Linen_US
dc.contributor.authorChun-Yu Linen_US
dc.contributor.authorShih-Chieh Changen_US
dc.date.accessioned2014-10-30T09:35:09Z
dc.date.available2014-10-30T09:35:09Z
dc.date.issued2009-11-24zh_TW
dc.identifierntnulib_tp_E0213_02_011zh_TW
dc.identifier.urihttp://rportal.lib.ntnu.edu.tw/handle/20.500.12235/36385
dc.languageenzh_TW
dc.relationProc. of International SOC Design Conference (ISOCC) (pp. 536-539), Busan, Korea.�en_US
dc.titleDesign and Verification for Dual Issue Digital Signal Processoren_US

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