Design and Verification for Dual Issue Digital Signal Processor
| dc.contributor | 國立臺灣師範大學科技應用與人力資源發展學系 | zh_tw |
| dc.contributor.author | Cheng-Hung Lin | en_US |
| dc.contributor.author | Chun-Yu Lin | en_US |
| dc.contributor.author | Shih-Chieh Chang | en_US |
| dc.date.accessioned | 2014-10-30T09:35:09Z | |
| dc.date.available | 2014-10-30T09:35:09Z | |
| dc.date.issued | 2009-11-24 | zh_TW |
| dc.identifier | ntnulib_tp_E0213_02_011 | zh_TW |
| dc.identifier.uri | http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/36385 | |
| dc.language | en | zh_TW |
| dc.relation | Proc. of International SOC Design Conference (ISOCC) (pp. 536-539), Busan, Korea.� | en_US |
| dc.title | Design and Verification for Dual Issue Digital Signal Processor | en_US |