Multi-bit Delta-Sigma Modulator Using a Modified DWA Algorithm
| dc.contributor | 國立臺灣師範大學電機工程學系 | zh_tw |
| dc.contributor.author | Chien-Hung Kuo | en_US |
| dc.contributor.author | Tzu-Chien Hsueh | en_US |
| dc.contributor.author | Shen-Iuan Liu | en_US |
| dc.date.accessioned | 2014-10-30T09:28:40Z | |
| dc.date.available | 2014-10-30T09:28:40Z | |
| dc.date.issued | 2002-12-01 | zh_TW |
| dc.description.abstract | A four pointer data weighted averaging (FPDWA) algorithm is presented to reduce the nonlinearity of the feedback multi-bit digital-to-analog converter (DAC) for delta-sigma modulators. By utilizing the proposed algorithm, the noise power caused by element mismatch can be reduced. A nine-level second-order delta-sigma modulator has been implemented in a double-poly double-metal 0.35 μm CMOS process. Experimental results indicate the peak SNDR reaches 86.59 dB within bandwidth of 22 kHz. The maximum input amplitude is −7 dB below the full scale with 10-kHz input frequency, the sampling frequency is 5 MHz, and the OSR is around 113. The power consumption is 6.27 mW for a power supply of 3.3 V. | en_US |
| dc.description.uri | http://link.springer.com/content/pdf/10.1023%2FA%3A1020769913779 | zh_TW |
| dc.identifier | ntnulib_tp_E0610_01_008 | zh_TW |
| dc.identifier.issn | 0925-1030 | zh_TW |
| dc.identifier.uri | http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/32207 | |
| dc.language | en | zh_TW |
| dc.publisher | Springer Verlag (Germany) | en_US |
| dc.relation | Analog Integrated Circuits and Signal Processing, 33(3), 289-300. | en_US |
| dc.title | Multi-bit Delta-Sigma Modulator Using a Modified DWA Algorithm | en_US |