Via minimization with associated constraints in three-layer routing problem
| dc.contributor | 國立臺灣師範大學資訊教育研究所 | zh_tw |
| dc.contributor.author | Fang, Sung-Chuan | en_US |
| dc.contributor.author | Chang, Kuo-En | en_US |
| dc.contributor.author | Feng, Wu-Shiung | en_US |
| dc.date.accessioned | 2014-10-30T09:32:14Z | |
| dc.date.available | 2014-10-30T09:32:14Z | |
| dc.date.issued | 1990-05-01 | zh_TW |
| dc.description.abstract | Via minimization is the same as the layer assignment problem in VLSI or PCB routing. It consists of determining which layers can be used for routing the wire segments such that the number of vias can be minimized. A heuristic algorithm is presented to globally eliminate the vias in the three-layer channel routing. Some associated constraints, such as restricted terminals and adjacent limitation, are addressed extensively. According to the results, the algorithm is fast and efficient, thus generating very good results. | en_US |
| dc.description.uri | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=112450 | zh_TW |
| dc.identifier | ntnulib_tp_A0904_02_006 | zh_TW |
| dc.identifier.uri | http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/34398 | |
| dc.language | en | zh_TW |
| dc.relation | Proceedings of IEEE/ACM International Symposium on Circuits and Systems(ISCAS90), New Orleans, Louisiana. (pp. 1632-1635) | en_US |
| dc.relation.uri | http://dx.doi.org/10.1109/ISCAS.1990.112450 | zh_TW |
| dc.title | Via minimization with associated constraints in three-layer routing problem | en_US |