金屬/氧化鉿(HfO2)/氧化釩(VO2)/氧化鉿(HfO2)/Si 結構應用於MOSFET之電性研究

Abstract

隨著現代科技產品朝向輕、薄、功能性多以及多樣化結合的發展，使得電子產品的製造商對於半導體元件的要求變更加嚴格，因此對於電晶體的品質要求也隨之變高。本研究使用了高功率脈衝磁控濺鍍技術(HIPIMS)來製作鋁(Al)/二氧化鉿(HfO2)/二氧化釩(VO2)/二氧化鉿(HfO2)/Si之MIS結構，有別於傳統的直流磁控濺鍍技術，高功率脈衝磁控濺鍍技術能更有效率的製作薄膜。本研究採以不同的VO2薄膜厚度(20 nm、40 nm、60 nm)，以及不同的退火溫度(500 ºC、650 ºC、800 ºC)退火60秒，使用半導體分析儀量測電流-電壓 (I - V)和電容-電壓(C - V)特性，並分析不同厚度和退火溫度所造成的影響。最後，會進一步的量測電容-電壓(C - V)電特性量測進行介面陷阱電荷(Dit)的量測，探討不同的參數對於漏電流以及界面陷阱密度(Dit)的影響。我們在各個退火溫度與薄膜厚度的關係中可以發現，當薄膜厚度在20 nm 的時候退火溫度越高，漏電流越大，而當薄膜厚度在40、60 nm時，退火溫度越高，漏電流反而更小，推測是材料內部的結晶重新排列消除了大部分的缺陷，而退火溫度太低還沒到達再結晶溫度，因此漏電流會隨著厚度增加。進行了界面陷阱電荷密度(Dit)量測，我們在各個退火溫度與薄膜厚度的關係中可以發現與電性量測時相同的趨勢，在20 nm的時候退火溫度越高，陷阱越大，而當薄膜厚度在40、60 nm 時，退火溫度越高，陷阱反而更小，而在這之中比較出最好的數值是800 ºC的退火溫度，厚度40 nm的試片，會形成這樣的結果推測是因為厚度在40 nm 時有較好的薄膜反應並且有將缺陷以及應力消除。Owing to the development of modern technology products towards light, thin, multi-functional and diversified combinations, manufacturers of electronic products have become more stringent on semiconductor components, and the quality requirements on transistors have also become higher and higher. In this study, HIPIMS was used to fabricate the Al/HfO2/VO2/HfO2/Si (MIS) structures. HIPIMS was different from the traditional DC magnetron sputtering technique. HIPIMS could make thin films more efficiently.This study has used different VO2 film thicknesses (20 nm, 40 nm, 60 nm) and different annealing temperatures (500 ºC, 650 ºC, 800 ºC) for 60 seconds. This study used a semiconductor to measure the I - V and C - V characteristics, and also analyzed the effects of different thicknesses and annealing temperatures. At last, the C - V electrical characteristics were further analyzed by the Dit. And the influence of different parameters on the leakage current and Dit were discussed.In the experiment, it could be found that when the film thickness was 20 nm, the higher the annealing temperature, the more the leakage current. And when the film thickness was 40 and 60 nm, the higher the annealing temperature, the less the leakage current, which was presumed to be the crystallization inside the material. The rearrangement of the film eliminated most of the defects, and the annealing temperature was too low to reach the recrystallization temperature, so the leakage current increased with thickness.The interfacial trap charge density (Dit) measurement was carried out. The same trend as the electrical measurement was found in the experiment. At 20 nm, the higher the annealing temperature, the more traps. When the film thickness was 40 nm and 60 nm, the higher the annealing temperature, the fewer traps. Moreover, among these different thicknesses, the best value was found at the annealing temperature of 800 ºC, the thickness of the test piece was 40 nm. The reason of this result was guessed that 40 nm thickness would create better film response and removal of defects and stress.