先進應變工程於奈米電子元件之模擬與實驗驗證

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2012

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本研究分析n型電晶體元件佈局圖對於元件之應力分佈與性能表現。該先進奈米元件之應力源主要由碳化矽材料填充於源∕汲極與具有拉伸應力之接觸蝕刻終止層組成;其中碳莫耳比例為1.65 %,接觸蝕刻終止層之拉伸應力為1.1 GPa。此研究提出一利用三維有限元素分析,模擬接觸蝕刻終止層之應力對於淺溝槽隔離上方的延伸閘極與元件通道之影響。模擬若以非製程方式考慮分析時,當延伸閘極之寬度為0.2 um時,元件載子遷移率增益之最大值約達72.5 %;分析結果指出若延伸閘極之寬度超過此尺寸,則接觸蝕刻終止層之機械應力將為元件性能表現之主要影響。若採以製程方式分析之,則當延伸閘極之寬度為0.2 um時,元件載子遷移率增益之最大值約達77.5 %,該模擬結果與相關文獻之分析趨勢符合。 另一方面,本研究亦分別以二維與三維有限元素模型採用製程順序步驟之模擬法,分析具有矽鍺通道結合接觸蝕刻終止層結構之n型電晶體元件;其中接觸蝕刻終止層分別為拉伸應力為1.1 GPa與壓縮應力-2.0 GPa。分析時固定元件通道寬度為10 um並改變元件通道長度,以觀察元件通道內之應力分佈與電性性能表現。由於二維與三維模擬趨勢相互匹配,因此可以二維模擬簡化三維模擬。與元件通道寬度與長度之比例分別為10/0.11, 10/1, 10/10 (um/um)的情形下之電性測量結果相比較,發現元件通道之應力趨勢與電性測量結果相符。此外,藉由應力模擬與電性結果可得知,在較短元件通道長度時,拉伸應力之接觸蝕刻終止層可提升元件特性;而在較長通道長度時,則為壓縮應力之接觸蝕刻終止層對於元件表現有所提升。
In this study, the effect of layout of the n-type metal-oxide field-effect transistors (nMOSFET) on the stress distribution and performance of devices was analyzed. The nMOSFET is mainly composed of silicon–carbon (SiC) stressors embedded in the source and drain (S/D) regions with the carbon mole fraction of 1.65 % and a 1.1 GPa tensile contact etch stop layer (CESL), respectively. The stress contour of device induced by CESL and the protruding gate width on shallow trench isolation was discussed by the proposed three-dimensional (3D) finite element analysis (FEA) in this research. The results revealed that as the protruding gate width is approximately 0.2 m, the maximum carrier mobility gain is about 72.5 % under the consideration of non-process flow simulation. In contrast, the maximum gain of carrier mobility achieves close to 77.5 % by using the process-flow simulation technique. The above-mentioned results match well with the simulated trends reported in the relevant literatures. On the other hand, by means of two dimensional (2D) as well as 3D FEA process-flow simulations, the stress impacts of nMOSFETs resulted from CESL combined with the design of SiGe channel are performed. Two different stresses of CESL, 1.1 GPa and -2.0 GPa, with a fixed channel width of 10 m are used under the parametric study of channel length. The stress distribution of channel region could be completely observed during simulations. Owing to the FEA results of 2D are matched with 3D analysis, the simulated type could be simplified to 2D mode. As compared with the electrical properties measured by the 10/0.11, 10/1, and 10/10 (m/m) of ratios for the combinations of width and length in channel region, the analytic results point out that the electrical properties are corresponded with the stress trends. Consequently, a short channel length combined with a tensile CESL could enhance it device characteristics. Moreover, a long channel length integrated with a compressive CESL could improve its electrical performance, significantly.

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碳化矽源∕汲極, 接觸蝕刻終止層, 有限元素分析, 矽鍺通道, SiC S/D stressor, CESL, Finite element analysis, SiGe channel

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