結合CORDIC演算法之MIPS CPU設計與實作

Abstract

本論文為MIPS CPU結合CORDIC(COodinate Rotation DIgital Computer)演算法之研究,利用HDL(Hardware Description Language)硬體描述語言,實現具有三角函數運算指令之三十二位元MIPS CPU。設計結果經由ModelSim完成電路模擬,並下載至Xilinx Virtex XCV800 FPGA (Field Programmable Gate Array)功能驗證成功。由於CORDIC演算法有著運算快速和架構簡單的特性,近年來廣泛的被使用在DSP的相關應用上。對許多應用來說,微控制器搭配DSP處理晶片已經是相當經典的組合;而本論文在此提出使用CORDIC演算法結合MIPS的想法,期望在某些應用面比經典的方法更加合適(如僅需簡單的DSP處理指令),以達到節省成本的目的。本研究總共實作了三十七道固定點指令、四道浮點指令及兩道以CORDIC演算法為基礎的Cos和Sin運算指令。
This thesis is a study of embedding the CORDIC(COodinate Rotation DIgital Computer) algorithm into MIPS CPU design. Finally, a 32-bit MIPS CPU with trigonometric arithmetic instructions as well as a floating-point co-processor was implemented. The final design had been tested and simulated by ModelSim and verified by downloading into Xilinx Virtex XCV800 FPGA(Field Programmable Gate Array) successfully. The CORDIC algorithm had been utilized in many DSP applications recently because of its fast computation and simple hardware structure. The cooperation of a microcontroller and a DSP processor could be used in many DSP applications, but this thesis provides an alternation of embedding the CORDIC algorithm into MIPS CPU. We hope this combination will be more suitable in some simple applications, (like one may need only a few DSP instructions,) and achieves cost-down by this way. In this thesis, there are 37 fixed-point, 4 floating-point and 2 trigonometric(Cos and Sin) instructions, 43 instructions have been implemented totally.

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Keywords

MIPS, HDL, CPU, FPGA, CORDIC

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