應用於超低功率互補式傾斜閘極穿隧場效電晶體之設計

Abstract

基於物理限制的原因，金氧半場效電晶體(Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET)的次臨界擺幅無法低於60 mV/decade，使操作電壓Vdd無法持續往下微縮。穿隧型場效電晶(Tunnel Field Effect Transistor, TFET)近期受到許多研究團隊關注，由於不用同於金氧半場效電晶體操作機制，它是利用能帶至能帶的穿隧(Band-to-Band Tunneling)，因此能夠擁有低於60 mV/decade的次臨界擺幅，有利於操作電壓Vdd的微縮。 在本論文的研究，我們提出最大電場與最大能帶至能帶穿隧機率有相當的關聯性，以促使穿隧型場效電晶體元件性能進一步提升，利用半導體模擬工具 (Technology Computer Aided Design, TCAD)來應證。本文成功設計出穿隧電晶體由pTFET為矽鍺與矽、nTFET為砷化銦與銻化鎵所組成的互補式架構，且元件結構能使最大電場與最大能帶至能帶穿隧機率對齊，使穿隧機率大幅提升。模擬結果顯示在閘極形成一個鈍角的結構並搭配異質接面的方式，能使得元件相較於平面能有4個數量級的驅動電流值提升。最後，本研究的互補式傾斜閘極穿隧電晶體元件在適當角度的閘極結構下，能取代互補式金屬氧化半導體元件在低操作功率(Low Operation Power, LOP)及低待機功率(Low Standby Power, LSTP)操作狀態下的元件。Due to the physical limitation, the sub-threshold swing (S.S.) of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) can not be below 60 mV/decade, which limits the scaling of the operation voltage (Vdd). Tunneling FETs (TFETs) have been attracted much more attention because Zener band-to-band tunneling (B2BT) allows S.S. smaller than 60 mV/decade, and hence Vdd can be accordingly scaled down. In this research, we have proposed a new engineering concept for alignment between the maximum band-to-band tunneling rate and electric field that was designed to enhance the performance of TFETs, which has been demonstrated by Technology Computer Aided Design (TCAD). The structures of hetero junctions for pTFETs and nTFETs are SiGe/Si and InAs/GaSb, respectively. A novel structure of Tilt-Gate TFET has been introduced to increase the B2B tunneling probability by the exact alignment between maximum electric field and maximum B2BT rate. It was found that if the gate of TFET is formed an obtuse shape, the on-current can be dramatically improved by 4 orders in comparison with the planar transistors. Therefore, Tilt complementary TFET has been constructed and with its potential to replace the CMOS devices in LOP and LSTP applications by suitable design of the gate structure in the new design.