與14奈米鰭式電晶體CMOS邏輯製程相容的電阻式快閃記憶體設計

Abstract

傳統非揮發性記憶體如SONOS( Silicon-Oxide-Nitride-Oxide-Silicon )等的快閃記憶體有操作電壓高、隨機摻雜擾動( random dopant fluctuation )、穿隧氧化層厚度造成的漏電( charge loss )、隨機電報雜訊 (random telegraph noise )、寫抹不匹配( mismatch between program and erase )等先天微縮的限制，使嵌入式記憶體整合困難，學術界與產業界，無不投入大量資源，尋找下一世代的新興記憶體。

電阻式記憶體( Resistive Random Access Memory, RRAM )成為非揮發性記憶體的熱門研究方向，低功耗、低成本、易整合於後段製程與邏輯電路中，成為電阻式記憶體的優勢，並且因簡單的堆疊結構即可完成，甚至可有零光罩與現有邏輯CMOS製程整合的便利性，其潛力可見一斑。

另一方面，電阻式記憶體依操作方式又可分為單極性電阻式記憶體以及雙極性電阻式記憶體，不同的機制發生取決於上下電極的材料與介電層的材料，在本論文中的雙極性電阻式記憶體主要是價電轉換機制的類型，發生於14奈米鰭式電晶體之介電層，使用的上電極材料是TiN，介電層是使用高介電系數的二氧化鉿為基底之電阻式記憶體，下電極則是高濃度的半導體材料，形成一個特殊的金屬-氧化物-半導體( MIS ) 電阻式記憶體結構。

本論文成功的以閘極堆疊電阻式記憶體整合於14奈米鰭式電晶體之純CMOS ( Complementary Metal-Oxide-Semiconductor )邏輯製程平台，建構嵌入式記憶體。我們分別探討在n型電晶體與p型電晶體上RRAM的差異性；結果顯示本實驗可以在絕對值小於3V的電壓操作，電流的需求也小於1mA，在瞬時脈衝的操作下，僅需100 ns的時間即可轉態，另外在可靠度的測試中，pFinFET RRAM之高低組態差異( on/off ratio )也可以達到1000倍，並具有持續操作400次以上的耐久度( endurance )，nFinFET RRAM則可以維持至少150倍的記憶窗口，並持續1000次的操作耐久度，兩者也都可以在125℃的環境溫度下，保持一個月的穩定阻值。另外，我們針對干擾免疫( disturb immunity )做量測分析，控制電晶體也僅有些微的臨界電壓飄移。我們也將串聯電晶體作為限流，展示了記憶體具有多位元單胞的能力，使其有兩個位元( 2 bits )於同一個記憶胞中。

在陣列架構的討論上，我們設計一種新的架構，以主動鰭式電晶體阻隔( Active Fin Isolation, AFI )做為兩個儲存單元間的阻擋元件，搭配開關電晶體與記憶胞串聯( 1T1R )，取代傳統的交錯式陣列( crossbar array )，除了用電晶體來限制讀寫電流外，更有效的抑制溜徑電流( sneak current )，量測結果顯示新型陣列抑制了30%的電路預備功耗與接近99%的操作功耗，最後是電路干擾測試，結果顯示僅有些微的臨界電壓改變及電阻值的變化，而這些差異是幾乎可以忽略的。上述的實驗與模擬結果顯示本文提出的雙極性嵌入電阻式記憶體在先進製程嵌入式記憶體領域有極大的發展潛力。Traditional nonvolatile memory, such as SONOS Flash has disadvantages of high operating voltage, random dopant fluctuation, tunneling oxide induced leakage, random telegraph noise, and the other scaling limitation. These shortcomings make integration difficult, so, numerous efforts have been made on looking for future generation emerging memory.

On the other hand, Resistive Random Access Memory ( RRAM ) has an advantage of low power consumption, easy integration in the BEOL ( Back End of Line ) and logic circuit. Because of a simple stacked structure can be completed, or even zero mask integration possible, RRAM has a great potential for better embedded memory applications.

RRAM is divided into two categories according to operation type: unipolar RRAM and bipolar RRAM. Different mechanisms occur depending on the material of the upper and lower electrodes and the material of the dielectric layer. The bipolar RRAM is used in our work. In this paper, the composition of the RRAM used in this study consists of a TiN top electrode and a transition metal oxide layer, and a highly doped semiconductor source region of FinFET, with an underlap underneath the spacer.

In this work, we have demonstrated an oxygen-vacancy-based bipolar RRAM on a pure logic 14nm-node HKMG FinFET CMOS platform. The result has shown that RRAM can have low operation voltage (<3V ) and program within 100ns, also the demand for the maximum current is lower than 1mA. The reliability results have shown more than 400-time cycling for the endurance test and more than 1000-time window has been maintained for the retention test in the pFinFET RRAM. For the nFinFET RRAM, the reliability results have shown more than 1000-time cycling for the endurance test and more than 150-time window has been maintained for the retention test.

On the design of an RRAM memory array architecture, we used “active fin isolation” as a selector between two storage units. The transistor plays the role of switch, we put the switch and storage unit in series to replace the traditional crossbar architecture. In addition to using the transistor to limit the read and write current, sneak current can be suppressed efficiently. The simulation result shows that the new architecture can reduce a huge amount of power consumption and standby power. Especially, 30% and 99% reduction of the standby and active power have been also achieved, which shows the effective usage of the active-fin-isolation ( AFI ) in the FinFET RRAM array. Eventually, the disturbances of FinFET RRAM array during operation have also been investigated. The AFI and periphery RRAM close to the selected cell have been un-disturbed during the test. The selected control transistor has shown slightly increase of Vth shift, but this few increment will not hurt the driving capability for a control transistor to program the RRAM. These experimental and simulated results offer strong and solid results to elaborate the potential opportunities of the bipolar FinFET RRAM for embedded memories, especially for advanced CMOS technology node beyond 20nm.