Maximizing pin alignment in VLSI routing
| dc.contributor | 國立臺灣師範大學資訊教育研究所 | zh_tw |
| dc.contributor.author | 張國恩 | zh_tw |
| dc.contributor.author | 馮武雄 | zh_tw |
| dc.contributor.author | Chang, Kuo-En | en_US |
| dc.contributor.author | Feng, Wu-Shiung | en_US |
| dc.date.accessioned | 2014-10-30T09:32:07Z | |
| dc.date.available | 2014-10-30T09:32:07Z | |
| dc.date.issued | 1990-05-01 | zh_TW |
| dc.identifier | ntnulib_tp_A0904_01_004 | zh_TW |
| dc.identifier.issn | 0253-3839 | zh_TW |
| dc.identifier.uri | http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/34305 | |
| dc.language | en | zh_TW |
| dc.publisher | 中國工程師學會 | zh_tw |
| dc.relation | 中國工程學刊，13（1），103-114。 | zh_tw |
| dc.relation | Journal of the Chinese Institute of Engineers, 13(1), 103-114. | en_US |
| dc.title | Maximizing pin alignment in VLSI routing | en_US |