氧化釔摻鋯之堆疊高介電係數介電層應用於MOS電容之特性分析

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2012

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當電晶體的尺寸隨著趨勢逐漸微縮,傳統二氧化矽製成的閘極氧化層達到了物理極限,導致漏電流劇增。因此,高介電係數材料取代傳統二氧化矽做為閘極氧化層的文獻陸續被發表。氧化釔是一個有潛力的高介電係數材料,因為氧化釔的高介電係數(12-18)、寬的能隙(5.5 eV)、熱穩定度高,與矽的相容度很高,且跟矽的晶格不匹配的程度較低。不過氧化釔容易與矽產生擴散形成界面層。另外一方面,由於氧化鋯適合做為閘極氧化層的材料,但它的結晶溫度較低,在高溫製程後會容易有結晶的現象。基於上述,本研究選擇氧化釔做為基礎,摻雜鋯至氧化釔中,形成介電層。接著覆蓋一層氮化鋯,藉由氮化鋯的特性,做為一層阻擋層,希望能減少擴散的產生。最後鍍上一層鈦金屬,在不同溫度的快速熱退火之後,量測該電容器的電性與物性。實驗結果顯示摻雜鋯後,會使高介電係數介電層在高溫製程後會有結晶的現象產生,導致薄膜表面較粗糙;覆蓋一層氮化鋯,可以減少擴散現象的發生,但如果氮化鋯的厚度不足,還是會有擴散產生。
As the dimension of metal-oxide-semiconductor field effect transistor (MOSFET) devices continues to scale down, the gate leakage current increases accordingly because the traditional gate oxide gradually approaches its physical limit. Therefore, high-K materials have been proposed to replace SiO2 in the literature. Y2O3 is a promising high-K material because of its high dielectric constant (12-18), wide band gap (5.5 eV), stable thermal stability, chemical compatibility with Si and low lattice mismatch between Y2O3 and Si. However it is easy to form the interfacial layer because of the inter-diffusion between Y2O3 and Si. On the other hand, ZrO2 has also been reported to be a suitable material for gate dielectric layer though it starts to crystallize after high temperature process (ie. low crystallization temperature). Based on the above understanding, Zr is introduced into Y2O3 to form the gate dielectric layer, and ZrN is subsequently deposited to suppress the inter-diffusion. Finally, metal Ti is deposited to form the gate. In this work, electrical characteristics and physical properties have been studied for the samples after rapid thermal annealing at different temperatures. The experimental results show that the Zr-incorporated Y2O3 thin film crystallizes and results in a rougher surface after a high temperature process.Moreover the ZrN layer can suppress inter-diffusion; however, the inter-diffusion still occurs if the ZrN layer is not thick enough.

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電晶體, 高介電係數, 氧化釔, 氮化鋯, MOSFET, high-K, Y2O3, ZrN

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