具無可複製功能的二位元單次編程記憶體的設計

Abstract

在單次寫入唯讀記憶體元件的發展上，大部分的熔斷崩潰(fuse breakdown)元件結構都是採用狹窄的金屬線或聚矽化物金屬絲進行操作，反熔斷崩潰(anti-fuse breakdown)元件則是在施加一個大的外部電場之後於介電層內形成永久的導通路徑。在高介電金屬閘極鰭式電晶體元件上，我們研究群在2015年發表過世界上首次觀察到有別於在平面型電晶體上的介電層熔斷崩潰(dielectric fuse breakdown)現象，本文以實驗來了解fuse 及anti-fuse崩潰機制類型的特性差異來組成二位元單次寫入記憶體(2-bit per cell One Time Programming memory)，進而發展成物理上無法複製的Physical Unclonable Function, PUF)記憶體的實現。 首先介紹我們的記憶單元，我們利用反熔斷崩潰( anti-fuse breakdown )及介電層熔斷崩潰兩種現象存在於一個元件內，並利用其崩潰後產生的高低阻態來達成資料儲存的目的，且利用TCAD模擬軟體模擬對元件進行編程時產生的電場分布，探討兩種崩潰現象產生的原因，另外還進行了改變操作電壓對編程時間造成的改變，以及溫度對於兩種崩潰機制造成的影響。 最後，根據這個新的物理機制，我們設計出基於二位元單次寫入記憶體的PUF電路，透過在單一元件儲存二位元的設計可以大大縮小晶片面積達到高密度，並且與其他文獻發表的成果相比下有較大的開/關電流比。量測結果也顯示這樣的結構仍然可以有良好的資料保存特性、干擾免疫特性以及高安全性。最後，我們成功的在14奈米鰭式電晶體製程平台實現一個二位元單次編程的PUF電路，以滿足物聯網之需求。

In the history of the development of OTP memory, many existing structures of fuse breakdown devices used a narrow wire of metal or poly-silicide wire. On the other hand, anti-fuse breakdown devices formed an electrically conductive path permanently in the dielectric after a large external electric field applying on the gate. Based on a dielectric fuse breakdown that was discovered in our research group, further applications have been employed in the application of nonvolatile memory on a FinFET platform. In this work, we use the experiments to understand the difference in the characteristics of the fuse and anti-fuse breakdown mechanisms and by taking this advantage to develop a 2-bit-per-cell OTP memory with Physically Unclonable Function. First, our memory cell consists of two breakdown mechanism in one cell including anti-fuse breakdown and dielectric fuse breakdown, which are used to achieve the purpose of data storage. Furthermore, we use the TCAD simulation to investigate the electric field distribution of the device when it operates in a high voltage, and discuss the reason of two breakdown phenomenon occurs in one device. We also try to vary the supply voltage and temperature to investigate the corresponding programming time in two breakdown mechanisms. Finally, based on this new scheme, we designed a novel 2-bit-per-cell OTP PUF, which has a larger on/off current ratio compared to that of reported results. Using the 2-bit-per-cell device can dramatically decrease the layout area and achieve high density. The experimental results show that this architecture still has excellent data retention, disturb immunity, and high security. Finally, a 2-bit-per-cell OTP PUF has been demonstrated successfully on a 14nm FinFET platform to meet the requirements of security applications in IoT era.