Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems

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dc.contributor國立臺灣師範大學資訊教育研究所zh_tw
dc.contributor.authorFang, Sung-Chuanen_US
dc.contributor.authorChang, Kuo-Enen_US
dc.contributor.authorFeng, Wu-Shiungen_US
dc.contributor.authorChen, Sao-Jieen_US
dc.date.accessioned2014-10-30T09:32:14Z
dc.date.available2014-10-30T09:32:14Z
dc.date.issued1991-03-01zh_TW
dc.description.urihttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=979689zh_TW
dc.identifierntnulib_tp_A0904_02_008zh_TW
dc.identifier.isbn0-89791-395-7zh_TW
dc.identifier.urihttp://rportal.lib.ntnu.edu.tw/handle/20.500.12235/34400
dc.languageenzh_TW
dc.relationProceedings of IEEE/ACM 28th Design Automation Conference. (pp. 60-65)en_US
dc.relation.urihttp://dx.doi.org/10.1109/DAC.1991.979689zh_TW
dc.subject.othervia minimizationen_US
dc.subject.otherlayer assignmenten_US
dc.subject.otherVLSI/PCB routingen_US
dc.subject.otherNP-completeen_US
dc.titleConstrained via minimization with practical considerations for multi-layer VLSI/PCB routing problemsen_US

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