Please use this identifier to cite or link to this item: http://rportal.lib.ntnu.edu.tw:80/handle/77345300/36373
Title: Efficient Pattern Matching Algorithm for Memory Architecture
Authors: 國立臺灣師範大學科技應用與人力資源發展學系
Cheng-Hung Lin
Shih-Chieh Chang
Issue Date: 1-Jan-2011
Abstract: Network intrusion detection system is used to inspect packet contents against thousands of predefined malicious or suspicious patterns. Because traditional software alone pattern matching approaches can no longer meet the high throughput of today's networking, many hardware approaches are proposed to accelerate pattern matching. Among hardware approaches, memory-based architecture has attracted a lot of attention because of its easy reconfigurability and scalability. In order to accommodate the increasing number of attack patterns and meet the throughput requirement of networks, a successful network intrusion detection system must have a memory-efficient pattern-matching algorithm and hardware design. In this paper, we propose a memory-efficient pattern-matching algorithm which can significantly reduce the memory requirement. For Snort rule sets, the new algorithm achieves 21% of memory reduction compared with the traditional Aho-Corasick algorithm. In addition, we can gain 24% of memory reduction by integrating our approach to the bit-split algorithm which is the state-of-the-art memory-based approach.
URI: http://rportal.lib.ntnu.edu.tw/handle/77345300/36373
ISSN: 1063-8210
Other Identifiers: ntnulib_tp_E0213_01_004
Appears in Collections:教師著作

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