Please use this identifier to cite or link to this item: http://rportal.lib.ntnu.edu.tw:80/handle/77345300/36372
Title: Optimization of Pattern Matching Circuits for Regular Expression on FPGA
Authors: 國立臺灣師範大學科技應用與人力資源發展學系
Cheng-Hung Lin
Chih-Tsun Huang
Chang-Ping Jiang
Shih Chieh Chang
Issue Date: 1-Dec-2007
Abstract: Regular expressions are widely used in the network intrusion detection system (NIDS) to represent attack patterns. Previously, many hardware architectures have been proposed to accelerate regular expression matching using field-programmable gate array (FPGA) because FPGAs allow updating of new attack patterns. Because of the increasing number of attacks, we need to accommodate a large number of regular expressions on FPGAs. Although the minimization of logic equations has been studied intensively in the area of computer-aided design (CAD), the minimization of multiple regular expressions has been largely neglected. This paper presents a novel sharing architecture allowing our algorithm to extract and share common subregular expressions. Experimental results show that our sharing scheme significantly reduces the area of pattern matching circuits for regular expression.
URI: http://rportal.lib.ntnu.edu.tw/handle/77345300/36372
ISSN: 1063-8210
Other Identifiers: ntnulib_tp_E0213_01_003
Appears in Collections:教師著作

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