Please use this identifier to cite or link to this item: http://rportal.lib.ntnu.edu.tw:80/handle/77345300/34505
Title: MCM電子構裝佈局設計自動化---子計畫五:適用於MCM之限制性穿孔減少
Constrained Via Minimization for Multichip Modules. (I)
Authors: 國立臺灣師範大學資訊教育研究所
張國恩
Issue Date: 1-Jul-1997
Abstract: 佈線中的限制性穿孔減少(Constrained via minimization,簡稱CVM)問題是探討如何決定佈局中各線段(Segments)所處的佈局層(Layer),使得所產生的穿孔數最少。本計畫嘗試將CVM問題轉換成圖形的縮減問題,然後按照所建的圖形縮減模式設計出相關的演算法以解決此問題。計畫中的方法曾用在VLSI的通道佈線上 (Channel routing),並得到相當好的結果。在計畫中嘗試將該方法用到PCB/MCM的應用上。由於PCB與MCM的設計與VLSI不同,故所考慮的限制也不同,因此PCB/MCM的穿孔減少問題是值得探討的。本計畫已完成初步的程式設計,並繼續推導理論使能考慮在MCM設計中Distribution vias,Stacked vias與Interconnection vias之特性。
The constrained via minimization (CVM) problem for MCM routing is the problem of determining which layers can be used for routing the wire segments in the interconnections of nets so that the number of vias is minimized. In this project, we first transform the problem of CVM for multilayer MCM routing to the graph contractability problem and then a heuristic algorithm is proposed on the basis of the graph contractability model. The project has completed the implementation of via minimization algorithm under WINDOW environment. The project will continuously address the theories for meeting the requirements in the MCM design and consider the constraints of distribution vias, stacked vias, and interconnection vias.
URI: http://rportal.lib.ntnu.edu.tw/handle/77345300/34505
Other Identifiers: ntnulib_tp_A0904_04_017
Appears in Collections:教師著作

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