Please use this identifier to cite or link to this item: http://rportal.lib.ntnu.edu.tw:80/handle/77345300/32249
Title: A 20 to 24 GHz +16.8-dBm fully integrated power amplifier using 0.18-痠 CMOS process
Authors: 國立臺灣師範大學應用電子科技學系
Yung-Nien Jen
Jeng-Han Tsai
Chung-Te Peng
Tian-Wei Huang
Issue Date: 1-Jan-2009
Publisher: IEEE Microwave Theory and Techniques Society
Abstract: A 20-24 GHz, fully integrated power amplifier (PA) with on-chip input and output matching is realized in 0.18 mum standard CMOS process. By cascading two cascode stages, the PA achieves 15 dB small signal gain, 10.7% power added efficiency, 16.8 dBm output saturation power and high power density per chip area of 0.137 W/mm2, which is believed to be the highest power density to our knowledge. The whole chip area with pads is 0.35 mm2, which is the smallest one compared to all reported paper.
URI: http://rportal.lib.ntnu.edu.tw/handle/77345300/32249
ISSN: 1531-1309�
Other Identifiers: ntnulib_tp_E0611_01_013
Appears in Collections:教師著作

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