Please use this identifier to cite or link to this item:
Title: A Multi-Band Delay-Locked LOOP with Fast-Locked and Jitter-Bounded Features
Authors: 國立臺灣師範大學電機工程學系
Chien-Hung Kuo
Meng-Feng Lin
Chien-Hung Chen
Issue Date: 5-Nov-2008
Abstract: In this paper, a multi-band delay-locked loop with fast-locked and jitter-bounded features is presented. A programmable charging voltage circuit to the loop filter is developed to accelerate the locking of DLL. The shortest lock time of the proposed DLL is six clock cycles from the unlocked state. In the presented DLL, two phase-frequency detectors with a tunable delay cell are used to reduce the output clock jitter. A new DLL-based frequency multiplier with less active devices is also proposed to promote the operating frequency range from 200 MHz to 2 GHz. The presented DLL is implemented in a 0.18 mum 1P6M CMOS process. The core area excluding PADs is 0.34times0.41 mm2. The power consumption of the presented DLL is 31.5 mW at a 1.8 V of supply voltage.
Other Identifiers: ntnulib_tp_E0610_02_008
Appears in Collections:教師著作

Files in This Item:
There are no files associated with this item.

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.