Please use this identifier to cite or link to this item:
Title: Multi-bit Delta-Sigma Modulator Using a Modified DWA Algorithm
Authors: 國立臺灣師範大學電機工程學系
Chien-Hung Kuo
Tzu-Chien Hsueh
Shen-Iuan Liu
Issue Date: 1-Dec-2002
Publisher: Springer Verlag (Germany)
Abstract: A four pointer data weighted averaging (FPDWA) algorithm is presented to reduce the nonlinearity of the feedback multi-bit digital-to-analog converter (DAC) for delta-sigma modulators. By utilizing the proposed algorithm, the noise power caused by element mismatch can be reduced. A nine-level second-order delta-sigma modulator has been implemented in a double-poly double-metal 0.35 μm CMOS process. Experimental results indicate the peak SNDR reaches 86.59 dB within bandwidth of 22 kHz. The maximum input amplitude is −7 dB below the full scale with 10-kHz input frequency, the sampling frequency is 5 MHz, and the OSR is around 113. The power consumption is 6.27 mW for a power supply of 3.3 V.
ISSN: 0925-1030
Other Identifiers: ntnulib_tp_E0610_01_008
Appears in Collections:教師著作

Files in This Item:
There are no files associated with this item.

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.