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Title: A 55-64 GHz fully-integrated sub-harmonic wideband transceiver in 130nm CMOS process
Authors: 國立臺灣師範大學應用電子科技學系
Jeng-Han Tsai
Issue Date: 1-Nov-2009
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Abstract: In this letter, a 55–64 GHz compact fully-integrated gigabit transceiver with sub-harmonic pump technique is presented. The transceiver consists of a single-pole-double-throw (SPDT) traveling wave switch, a low-noise amplifier (LNA), a buffer amplifier (BA), and two sub-harmonic resistive mixers for up-conversion and down-conversion, respectively. The transceiver using 130 nm standard CMOS technology achieves an up-conversion gain of 7.4 dB at 62 GHz and down-conversion gain of 7.2 dB at 60 GHz with a compact chip size of 1.2 . The 3 dB frequency bandwidth ranges from 55 to 64 GHz, which can cover the whole frequency band for 802.15.TG3C WPAN applications. For system applications, gigabit BPSK modulation signal test is successfully performed in this work.
ISSN: 1531-1309
Other Identifiers: ntnulib_tp_E0611_01_007
Appears in Collections:教師著作

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