Please use this identifier to cite or link to this item: http://rportal.lib.ntnu.edu.tw:80/handle/20.500.12235/110747
Title: 38 GHz可變增益放大器與單邊帶調變混頻器設計
Design of 38 GHz Variable Gain Amplifier and Single-Sideband Mixer
Authors: 蔡政翰
Tsai, Jeng-Han
林禎芳
Lin, Chen-Fang
Keywords: 互補式金氧半導體製程
可變增益放大器
電流控制架構
單邊帶調變混頻器
鏡像抑制
CMOS
Variable Gain Amplifier
Current Steering
Single-Sideband Mixer
Image Rejection Ratio
Issue Date: 2019
Abstract: 隨著毫米波頻段的發展,在相位陣列(Phase Array)架構的射頻收發器中,可變增益放大器及混頻器為重要的元件。由於互補式金氧半導體製程(CMOS)的進步,近年來已經可以將大部分的射頻電路整合在一起,且CMOS具有低功率消耗、低成本及高整合度的優勢,因此本論文將使用TSMC 65nm CMOS製程,設計實現38 GHz可變增益放大器與單邊帶調變混頻器。 第一個電路為38 GHz低相位變化之可變增益放大器,採用兩級的電流控制架構(Current Steering),透過數位控制與相位補償技術,來維持在可變增益範圍內的低相位變化,及降低系統控制複雜度。當供應電壓Vdd為2 V,Vg1、Vg2分別為0.6 V、1.6 V時,在38 GHz有最高增益17.67 dB,可變增益範圍則是在2.61 dB ~ 17.67 dB,約有15.06 dB,相位差為2.69°,1-dB增益壓縮點之輸出功率OP1dB約為-0.68 dBm,整體功率消耗約為56.77 mW,整體晶片佈局面積為460 μm × 680 μm。 第二個電路為38 GHz單邊帶調變混頻器,藉由給予兩顆混頻器正交訊號,將兩個相差180°的輸出訊號合成後,會達到鏡像抑制之功能。由於我們使用來產生正交訊號的多相位濾波器(Poly Phase Filter),對於製程變異相當敏感,因此最後實現的單邊帶調變混頻器有頻飄的狀況。當電晶體偏壓為0.4 V,LO驅動功率為3 dBm時,頻帶為31 ~ 40 GHz,增益範圍為-16.3 ± 0.5 dB,鏡像抑制則有35 dB,整體晶片佈局面積為710 μm × 770 μm。
As the progress of the millimeter-wave band, variable gain amplifiers (VGA) and mixers play an important role in the phased-array radio frequency transceiver. Recently, the RFcircuits have been into the Complementary Metal-Oxide Semiconductor (CMOS) process. And using the CMOS topology has the advantages of low power consumption, low cost and high integration. In this paper, 38 GHz VGA and single-sideband mixer (SSB Mixer) are presented, and implemented in TSMC 65nm CMOS technology. First, a 38 GHz low phase variation VGA has designed and implemented. The circuit adopted two current steering stages. To maintain low phase variations over the variable gain range and reduce system control complexity, we utilized digital control and phase compensation techniques. When the supply voltage is 2 V, Vg1 and Vg2 is 0.6 V and 1.6 V, the VGA has a peak gain of 17.67 dB at 38 GHz. The variable gain range is from 2.61 dB to 17.67 dB with a range of 15.06 dB, and the phase error is 2.69 °. The output power of -0.68dBm at 1-dB gain compression point. The DC power consumption is 56.77 mW, and the chip size is 460 μm × 680 μm. Second, a 38 GHz SSB Mixer has designed and implemented. By giving two mixer quadrature signals, the two output signals with 180° difference are combined to achieve the image suppression function. However, the poly phase filter which we use to be quadrature phase generator is sensitive to the process variation. Therefore, the SSB Mixer frequency shifted. When the bias is 0.4 V and LO drive power is 3 dBm, the gain range is -16.3 ± 0.5 dB from 31 to 40 GHz and the IRR is 35 dB. The chip size is 710 μm × 770 μm.
URI: http://etds.lib.ntnu.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=id=%22G060675005H%22.&%22.id.&
http://rportal.lib.ntnu.edu.tw:80/handle/20.500.12235/110747
Other Identifiers: G060675005H
Appears in Collections:學位論文

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