電機工程學系

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歷史沿革

本系成立宗旨在整合電子、電機、資訊、控制等多學門之工程技術，以培養跨領域具系統整合能力之電機電子科技人才為目標，同時配合產業界需求、支援國家重點科技發展，以「系統晶片」、「多媒體與通訊」、與「智慧型控制與機器人」等三大領域為核心發展方向，期望藉由學術創新引領產業發展，全力培養能直接投入電機電子產業之高級技術人才，厚植本國科技產業之競爭實力。

本系肇始於民國92年籌設之「應用電子科技研究所」，經一年籌劃，於民國93年8月正式成立，開始招收碩士班研究生，以培養具備理論、實務能力之高階電機電子科技人才為目標。民國96年8月「應用電子科技學系」成立，招收學士班學生，同時間，系所合一為「應用電子科技學系」。民國103年8月更名為「電機工程學系」，民國107年電機工程學系博士班成立，完備從大學部到博士班之學制規模，進一步擴展與深化本系的教學與研究能量。

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系所網址：https://www.ee.ntnu.edu.tw/

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Author: search.filters.author.Jeng-Han TsaiSubject: search.filters.subject.linearizer

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Now showing 1 - 3 of 3
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    A miniature 38-48 GHz MMIC sub-harmonic transmitter with post-distortion linearization
    (2007-06-08) Jeng-Han Tsai; Tian-Wei Huang
    This paper presents a miniature 38-48 GHz sub-harmonic transmitter with post-distortion linearization using a 0.15-mum GaAs HEMT process. The transmitter, which integrates a sub-harmonic mixer, a band-pass driver amplifier, and a linearizer, has a compact chip size of 2.5 mm2 with conversion gain of 7 plusmn 1.5 dB from 38 to 48 GHz. With the features of the sub-harmonic mixer and band-pass driver amplifier, the 2fLO leakage rejection of the transmitter is 47 dB. For the linearity of the transmitter, a post-distortion linearizer is added. After linearization, the output spectrum re-growth can be suppressed by 8 dB at 40 GHz. To keep ACPR below -35 dBc, the output power has been increased from -2 to 1 dBm, which means the linear output power has been doubled after linearization.
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    A 24-GHz 3.8-dB NF Low-Noise Amplifier with Built-In Linearizer
    (2010-12-10) Yen-Hung Kuo; Jeng-Han Tsai; Wei-Hung Chou; Tian-Wei Huang
    A K-band low-noise amplifier with built-in linearizer using 0.18-μm CMOS technology is presented in this paper. To achieve good linearity at high frequency, a distributed derivative superposition linearization technique is used. The measured results show that the improvement of IIP3 and IM3 are 5.3 dB and 10.6 dB at 24 GHz, respectively. The proposed LNA has a noise figure of 3.8 dB and a peak gain of 13.7 dB while consuming 18 mW dc power. To the best of our knowledge, this is the first LNA with a built-in linearizer above 20 GHz in CMOS.
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    A 60-GHz CMOS power amplifier with built-in pre-distortion linearizer
    (Institute of Electrical and Electronics Engineers (IEEE), 2011-12-01) Jeng-Han Tsai; Chung-Han Wu; Hong-Yuan Yang; Tian-Wei Huang
    A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power ampli- fier (PA) achieves a of 10.72 dBm and of 7.3 dBm from 1.2 V supply. After linearization, the has been doubled from 7.3 to 10.2 dBm and the operating PAE at consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.