教師著作

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Subject: search.filters.subject.CMOS

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Now showing 1 - 10 of 28
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    24 GHz CMOS 收發器線性化技術
    (行政院國家科學委員會, 2009-07-31) 蔡政翰
    本計畫將開發應用於下一代寬頻高速的無線通信系統的24GHz 高線性度收發器積 體電路，實現的方法將使用互補式金氧半導體之積體電路技術。計畫目標是研究利用矽 基製程技術，開發24GHz 收發器積體電路，包括功率放大器、低雜訊放大器、與混頻 器等。並且爲了滿足現今高速無線數位通信系統嚴格的線性度要求，本計畫針對發射器 中的關鍵元件，作線性度的分析，並且發展線性化技術，達到在有限的電能消耗下，設 計一24GHz CMOS 高線性度收發器的目標。
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    A 30-60GHz CMOS sub-harmonic IQ de/modulator for high data-rate communication system applications
    (2009-01-22) Wei-Heng Lin; Wei-Lun Chang; Jeng-Han Tsai; Tian-Wei Huang
    A 30-60 GHz sub-harmonic IQ de/modulator using TSMC CMOS 0.13-mum process is presented in this paper. The IQ de/modulator consists of two FET resistive mixers, a 90deg coupler, and a Wilkinson power divider. The resistive mixer could simultaneously used as a up-converted or a down-converted mixer. Therefore, the measurement of the FET resistive mixer based modulator or demodulator will be done. The die size is 0.78 mm times 0.58 mm. Both IQ demodulator and modulator feature the conversion loss of -16plusmn1 dB and good demodulation and modulation capacity.
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    A 50-to-62GHz wide-locking-range CMOS injection-locked frequency divider with transformer feedback
    (2008-06-17) Yu-Hang Wong; Wei-Heng Lin; Jeng-Han Tsai; Tian-Wei Huang
    A 50-to-62 GHz injection-locked frequency divider (ILFD) with transformer feedback technique is designed in 0.13-mum CMOS technology for wide locking range. The measurement results show that the free-running frequency is 55.3 GHz and the total locking range is 12 GHz (>20%) at the input power level of 0 dBm while consuming 10.8 mW from a 0.9 V power supply. The phase noise of the divider is -124.93 dBc/Hz at 1 MHz offset from the carrier. This wide locking range ILFD is suitable for integration into a phase-lock-loop (PLL) system because of its small size and no need of extra control signal.
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    A V-band fully-integrated CMOS distributed active transformer power amplifier for 802.15.TG3c wireless personal area network applications
    (2008-10-15) Yung-Nien Jen; Jeng-Han Tsai; Tian-Wei Huang; Huei Wang
    A 60-GHz fully-integrated and broadband distributed active transformer (DAT) power amplifier (PA) is implemented in 90-nm CMOS technology. The PA performs a flat small signal gain of 26 plusmn 1 dB from 57 to 69 GHz which covers full band for 60-GHz wireless personal network (WPAN) applications. By using the DAT output combine structure, this PA delivers 18-dBm measured output power with 12.2% PAE at 60 GHz with a compact chip size. To the best of our knowledge, this DAT CMOS PA demonstrates the highest output power among the reported 60-GHz CMOS PAs to date.
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    A 90-nm CMOS broadband and miniature Q-band balanced medium power amplifier
    (2007-06-08) Jeng-Han Tsai; Yi-Lin Lee; Tian-Wei Huang; Cheng-Ming Yu; John G. J. Chern
    This paper presents a Q-band balanced medium power amplifier fabricated using standard 90-nm 1P9M CMOS technology. The balanced amplifier, which is constructed with two broadband amplifiers and two broadside couplers using thin-film microstrip (TFMS) line technique, has a compact chip size of 0.78 x 0.92 mm2. The MMIC demonstrates a measured gain of 14.5 dB at 48 GHz. With the feature of the balanced amplifier, the MMIC has a 3-dB bandwidth up to 37.2 % from 35 to 51 GHz with flat gain and return loss frequency response. Furthermore, the balanced amplifier delivers a saturation output power of 10.6 dBm with 8% PAE and OPldB is 7.5 dBm.
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    A 68-83-GHz power amplifier in 90 nm standard CMOS
    (2009-06-12) Jeffrey Lee; Chung-Chun Chen; Jeng-Han Tsai; Kun-You Lin; Huei Wang
    A balanced PA covering 68-83 GHz is developed in 90 nm CMOS. Using wideband power matching topology, the PA achieves power gain of greater than 18.1 dB from 68 to 83 GHz and gain flatness within 0.2 dB from 68 to 78 GHz. The PA has a maximum saturation output power of 14 dBm at 70 GHz, and greater than 11.8 dBm from 68 to 83 GHz. The best P1dB is 12 dBm at 68 GHz, and greater than 8.3 dBm from 68 to 83 GHz.
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    A 25-75-GHz broadband Gilbert-cell mixer using 90-nm CMOS technology
    (IEEE Microwave Theory and Techniques Society, 2007-04-01) Jeng-Han Tsai; Pei-Si Wu; Chin-Shen Lin; Tian-Wei Huang; John G.J. Chern; Wen-Chu Huang; Huei Wang
    A compact and broadband 25-75-GHz fully integrated double-balance Gilbert-cell mixer using 90-nm standard mixed-signal/radio frequency (RF) CMOS technology is presented in this letter. A broadband matching network, LC ladder, for Gilbert-cell mixer transconductance stage design is introduced to achieve the flatness of conversion gain and good RF port impedance match over broad bandwidth. This Gilbert-cell mixer exhibits 3plusmn2dB measured conversion gain (to 50-Omega load) from 25 to 75GHz with a compact chip size of 0.30mm2. The OP1 dB of the mixer is 1dBm and -4dBm at 40 and 60GHz, respectively. To the best of our knowledge, this monolithic microwave integrated circuit is the highest frequency CMOS Gilbert-cell mixer to date
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    A V-band VCO using fT-doubling technique in 0.18-μm CMOS
    (2011-12-08) Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang; Huei Wang
    A low supply voltage V-band voltage-controlled oscillator (VCO) using fT-doubling technique is presented in this paper. The proposed VCO is fabricated in 0.18-μm CMOS technology. The proposed VCO adopts the fT-doubling technique to eliminate the gate-to-source capacitance of cross-coupled pair of VCO. The oscillation frequency of VCO can be increased due to the parasitic capacitance is eliminated. The measured results show that the proposed VCO have tuning range of 0.74 GHz from 58.09-to-58.83 GHz. The proposed VCO consumes 4 mW dc power from 1.2 V supply voltage.
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    Admittance-Transforming Injection-Locked Frequency Divider and Low-Supply-Voltage Current Mode Logic Divider
    (2010-12-10) Yen-Hung Kuo; Jeng-Han Tsai; Wei-Hung Chou; Tian-Wei Huang
    A injection-locked frequency divider (ILFD) with a 0.8-V current mode logic (CML) frequency divider are presented in this paper. These two frequency dividers are fabricated and integrated in 0.13-μm CMOS technology. The proposed ILFD adopts the admittance-transforming to widen the locking range. To achieve low-supply-voltage in CML frequency divider, the transconductance stage of CML divider is replaced by the inductance. Under 0 dBm injected power, the measured results show that the proposed ILFD have 22.8 % bandwidth from 40.5-to-50.9 GHz. Furthermore, the divider-by-four frequency divider composed of an ILFD and CML divider are measured with locking range from 42 to 45 GHz. The ILFD and CML divider consume 3.6 mW and 8 mW dc power from 0.6 V and 0.8 V supply voltage, respectively.
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    An ultra low-power 24 GHz phase-lock-loop with low phase-noise VCO embedded in 0.18-μm CMOS process
    (2011-12-08) Yu-Hsuan Lin; Jeng-Han Tsai; Yen-Hung Kuo; Tian-Wei Huang
    A 24 GHz 29.8 mW Phase-lock-loop using 0.18 μm CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by -122 dBc/Hz at 10 MHz offset with low supply voltage and equipped the locking range of 20.80-23.37 GHz. The PLL dissipate 29.8 mW (only 13.3 mW in VCO + ILFD) and occupies the total area of 0.39 mm2 without off-chip loop filter.